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PRELIMINARY
QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL RECEIVER
ICS853017
GENERAL DESCRIPTION
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V difIC S ferential LVPECL/ECL receiver and a member of the HiPerClockSTM HiperclocksTM family of High Performance Clock Solutions from IDT. The ICS853017 operates with a positive or negative power supply at 2.5V, 3.3V or 5V, and can accept both single-ended and differential inputs. For singleended operation, an internally generated voltage, which is available on output pin VBB, can be used as a switching bias voltage on the unused input of the differential pair. VBB can also be used to rebias AC coupled inputs.
FEATURES
* Four differential LVPECL / ECL 1:1 receivers * Four differential LVPECL clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz (typical) * Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input * Output skew: TBD * Part-to-part skew: TBD * Propagation delay: 320ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
D0 nD0 Q0 nQ0
PIN ASSIGNMENT
VCC D0 nD0 D1 nD1 D2 nD2 D3 nD3 VBB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 VEE
D1 nD1
Q1 nQ1
D2 nD2
Q2 nQ2
D3 nD3
ICS853017
Q3 nQ3
VBB
20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2 3 4 5 6 7 8 9 10 11 12, 13 14, 15 17, 18 19, 20 Name VCC D0 nD0 D1 nD1 D2 nD2 D3 nD3 VBB VEE nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Input Input Input Input Input Power Power Output Output Output Output Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Type Description Core supply pins. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Bias Voltage. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs D0:D3 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nD0:nD3 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIG H HIGH LOW Outputs nQ0:nQ3, HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sing/Source, IBB Storage Temperature, TSTG
(Junction-to-Ambient)
5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These -5.5V (ECL mode, VCC = 0) ratings are stress specifications only. Functional operation of -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C Package Thermal Impedance, JA 46.2C/W (0 lfpm)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V
Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3. 3 46 Maximum 5.25 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL V BB V PP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 D0, D1, D2, D3 Input Low Current nD0, nD1, nD2, nD3 2.075 1.43 1.86 800 1.2 3.3 200 -1 0 -10 1.2 Min -40C Typ 2.275 1.545 2.075 1.43 1.86 800 3.3 200 -10 -150 1.2 Max Min 25C Typ 2.295 1.52 2.075 1.43 1.86 800 3.3 200 Max Min 85C Typ 2.33 1.535 Max Units V V V V V mV V A A A
-150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
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ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 Input Low Current D0, D1, D2, D3 1.275 0.63 800 1.2 2.5 200 -10 -10 1.2 -40C Min Typ 1.475 0.745 1.275 0.63 800 2.5 200 -10 -150 1.2 Max Min 25C Typ 1.495 0.72 1.275 0.63 800 2.5 200 Max Min 85C Typ 1.53 0.735 Max Units V V V V mV V A A A
nD0, nD1, nD2, nD3 -150 -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1, nD2, nD3 Input Low Current D0, D1, D2, D3 3.775 3.13 80 0 1.2 5 200 -10 -10 1.2 -40C Min Typ 3.975 3.245 3.775 3.13 800 5 200 -10 -200 1.2 Max Min 25C Typ 3.995 3.22 3.775 3.13 800 5 200 Max Min 85C Typ 4.03 3.235 Max Units V V V V mV V A A A
nD0, nD1, nD2, nD3 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage, Single-Ended Input Low Voltage, Single-Ended Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0:D3, nD0:nD3 High Current Input Low Current D0:D3 -40C Min Typ -1.025 -1.755 -1.225 -1.87 -1.44 800 VEE+1.2V 0 20 0 -10 -10 VEE+1.2V -1.225 -1.87 -1.44 800 0 200 -10 -200 VEE+1.2V Max Min 25C Typ -1.005 -1.78 -1.225 -1.87 -1.44 800 0 200 Max Min 85C Typ -0.97 -1.765 Max Units V V V V V mV V A A A
nD0:nD3 -200 -200 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol fMAX t p LH t p HL t sk(o) t sk(pp) tR/tF Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% -40C Min Typ >2 320 320 TBD TBD 175
OR
VCC = 2.375V TO 5.25V; VEE = 0V
25C 85C Max Min Typ >2 320 320 TB D TBD 175 Max Min Typ >2 320 320 TBD TBD 175 Units GHz ps ps ps ps ps
Max
All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nD0:nD3
LVPECL
nQx VEE
V
PP
Cross Points
V
CMR
D0:D3
-3.5V to -0.375V
VEE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nD0:nD3 nD0:D3
80% Clock Outputs
80% VSW I N G
nQ0:nQ3 Q0:Q3
20% tR tF
20%
tp
LH
tp
HL
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
DX INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the Dx input to ground.
OUTPUTS:
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2
3.3V 3.3V
R4 125
3.3V Zo = 50 Ohm LVDS C1 R3 1K R4 1K PCLK
nPCLK
HiPerClockS PC L K /n PC LK
R1 1K
R2 1K
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 4A shows standard termination for 5V LVPECL. The termination requires matched load of 50 resistors pull down to V CC - 2V = 3V at the receiver. Figure 4B shows Thevenin equivalence of Figure 4A. In actual application where the 3V DC power supply is not available, this approached is normally used.
5V
5V 5V PECL Zo = 50 Ohm + Zo = 50 Ohm PECL
R1 125 R2 125 Zo = 50 Ohm PECL 5V R3 84 PECL Zo = 50 Ohm + R4 84
R1 50 3V
R2 50
FIGURE 4A. STANDARD 5V LVPECL OUTPUT TERMINATION
FIGURE 4B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853017. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853017 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 46mA = 253mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.94mW = 123.76mW
Total Power_MAX (5.5V, with all outputs switching) = 123.76mW + 253mW = 376.76mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 46.2C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.377W * 46.2C/W = 102.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.67V (VCC_MAX - VOL_MAX) = 1.67V
Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V
L
CC_MAX
- VOH_MAX))/R ] * (VCC _MAX- VOH_MAX) =
L
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V
L
CC_MAX
- VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) =
L
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
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ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853017 is: 187 Pin compatible with MC100EP58
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS853017AM ICS853017AMT ICS853017AMLF ICS853017AMLFT Marking ICS853017AM ICS853017AM TBD TBD Package 20 lead SOIC 20 lead SOIC 20 lead "Lead-Free" SOIC 20 lead "Lead-Free" SOIC Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
14
ICS853017AM REV. B OCTOBER 24, 2007
ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
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